1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit. More specifically, the present invention is directed to a technique effectively adaptable to a power MOS transistor having a current control function such as an overcurrent protection. For example, the present invention is directed to such a technique advantageously adaptable to either a power MOS transistor equipped with a composite function or a semiconductor switch having a composite function.
2. Description of the Related Art
Power MOS transistors have been widely used as, for example, power switches interposed between power sources and loads, capable of ON/OFF-controlling currents flowing therethrough. Conventionally, semiconductor integrated circuits have been provided on which such a power MOS transistor is formed on the same semiconductor substrate in combination with current control circuits capable of protecting overcurrents. This type of semiconductor integrated circuit is also referred to as an MOS transistor equipped with a composite function or a semiconductor switch having a composite function. For instance, when this semiconductor integrated circuit is used, both a conventional mechanical contact type switch function and a fuse (or overcurrent breaker) function may be collected into a single element, and also may be replaced by this semiconductor integrated circuit.
In order to provide user-friendly operation of this semiconductor integrated circuit in such a case that, for example, this semiconductor integrated circuit is employed as a replacement component of a conventional mechanical contact type switch, or in order to provide user-friendly operation as a single body of a power MOS transistor, this semiconductor integrated circuit is constructed in such a manner that only limited numbers of external terminals thereof are provided with respect to users. Concretely speaking, this semiconductor integrated circuit owns three terminals as external terminals (user terminals), namely, an output terminal, a control terminal, and a common terminal. When the respective terminals of the semiconductor integrated circuit are defined in correspondence with electrodes of a single body of an MOS transistor, the output terminal corresponds to the drain of this MOS transistor, the common terminal corresponds to the source thereof, and the control terminal corresponds to the gate thereof. A user connects both the output terminal and the common terminal in series to a current supply path between the power supply and the load, and also applies a control voltage between the control terminal and the common terminal, so that the user may turn ON/OFF the above-explained current supply path.
Generally speaking, an overcurrent protection circuit is employed as the current control circuit formed on the above-described semiconductor integrated circuit. As represented in FIG. 11, this overcurrent protection circuit is arranged by a current detecting circuit 10, a reference voltage generating circuit 20, a comparing circuit 30, and a gate control circuit 40. The current detecting circuit 10 converts a load current flowing between an output terminal P1 and a common terminal P3 into a corresponding voltage so as to detect this load current. The reference voltage generating circuit 20 generates a predetermined reference voltage. The comparing circuit 30 compares the current-detecting voltage of the current detecting circuit with the reference voltage. The gate control circuit 40 controls a gate voltage of a power MOS transistor based upon the comparison output of the comparing circuit 30.
In this case, in the above-explained current detecting circuit 10, a voltage dividing resistor element (shunt resistor) is provided in a current supply path of the load current, namely between the output terminal and the common terminal in such a manner that this voltage dividing resistor element is connected in series to a channel of an MOS transistor Q1 so as to convert the above-described load current into the voltage for detection purposes. Then, a current-detecting voltage is obtained from both ends of this voltage dividing resistor element.
As a result, between the output terminal and the common terminal of the above-explained semiconductor integrated circuit, an internal resistance may appear which is obtained by adding an ON-resistance (channel resistance) of the power MOS transistor to the resistance value of the voltage dividing resistor element. However, since this internal resistance may cause a voltage loss in the load current supply circuit, the resistance value of this internal resistance should be made lower as being permitted as possible. Very recently, while ON resistances of power MOS transistors could be reduced on the order of several milli-ohms, a major portion of this internal resistance could occupy the resistance value of the above-described voltage-dividing resistor element. In order that the current control operation such as the overcurrent protection is carried out while this internal resistance is made lower as being permitted as possible, the above-explained reference voltage must be set to a low voltage.
As to the reference voltage generating circuit, for instance, as shown as a reference in FIG. 12, such a circuit using a zener diode Dz is usually employed. Normally, the reference voltage (zener voltage) obtained from the zener diode Dz is higher than, or equal to approximately 6V, and therefore, this zener voltage cannot be directly used as the above-explained reference voltage. As a consequence, as shown in FIG. 12, this zener voltage of the zener diode is subdivided by using resistance elements R11 and R12 so as to obtain a predetermined lower reference voltage. There is one method for using a forward direction voltage of a diode which is lower than a zener voltage. However, since this forward direction voltage is equal to approximately 0.5V to 1V, this forward direction voltage is sub-divided by a resistor in the case that a reference voltage lower than this forward direction voltage is required.
However, the Inventors of the present invention could find out such a fact that the above-described techniques own the below-mentioned problems.
That is, since either the zener voltage of the zener diode or the forward direction voltage of the diode owns the large temperature dependent characteristic, there is such a problem that the stable reference voltage could not be obtained, and this stable reference voltage is required in order to correctly perform the current control operation such as overcurrent protections. This temperature dependent characteristic may be canceled by using, for example, such a temperature compensation realized by a band gap circuit. However, such a temperature compensation method may cause another problem that the band gap circuit becomes complex. However, there is a further serious problem. That is, in the above-described semiconductor integrated circuit equipped with the current control circuit, this semiconductor integrated circuit is made of such a circuit format that the operation voltages of the reference voltage generating circuit and of the comparing circuit may depend upon the control voltage for ON/OFF operations which is applied between the control terminal and the common terminal, the following restriction may exit. That is, the necessary reference voltage must be produced within the range of this control voltage.
In order to realize such a user-friendly operation as either the MOS transistor equipped with the composite function or the semiconductor switch having the composite function, this control voltage could not be obtained such a high voltage. To the contrary, this control voltage should be desirably made lower as being permitted as possible. When these aspects are considered, there is another problem. That is, in the reference voltage generating circuit shown in FIG. 12 using either the zener voltage of the zener diode or the forward direction voltage of the diode, the input voltage Vin required to generate the reference voltage could not be sufficiently obtained.
The present invention has been made to solve the above-explained problems, and therefore, has an object to provide such a semiconductor integrated circuit having an output terminal, a control terminal, and a common terminal, and capable of performing a current control such an overcurrent protection. That is to say, this semiconductor integrated circuit turns ON/OFF a path between the output terminal and the common terminal by way of a control voltage applied between the control terminal and the common terminal, and also detects such a current flowing through the path between this output terminal and this common terminal. In such a semiconductor integrated circuit, while a voltage loss occurred between the output terminal and the common terminal can be reduced, and further a user-sided apparatus load required to perform ON/OFF control operations can be reduced, the current control operation such as the overcurrent protection can be correctly carried out under stable condition.
The above-described object, other objects, and features of the present invention may become apparent from a detailed description of the specification and the accompanying drawings.
As means capable of solving the above-described problems, typically-used means among the inventive ideas disclosed in the present invention will be given as follows:
A first means is featured by such a semiconductor integrated circuit having an output terminal, a control terminal, and a common terminal, in which any one conductivity type MOS transistors, i.e., any one of p-channel type MOS transistors and n-channel type MOS transistors are formed in an integrated manner, wherein: a power MOS transistor, a current detecting circuit, a reference voltage generating circuit, a comparing circuit, and a gate controlling MOS transistor are formed on the same semiconductor substrate; and wherein: a drain of the power MOS transistor is connected to the output terminal, a gate thereof is connected to the control terminal, and a source thereof is connected to the common terminal; and also the power MOS transistor controls a current supplied between the output terminal and the common terminal in response to a control voltage applied to the control terminal; the current detecting circuit converts the current into a voltage; the reference voltage generating circuit has one pair of MOS transistors which are commonly connected to each other in such a manner that at least gate-to-source threshold voltages are equivalently made different from each other, and drains and gates of the paired MOS transistors become the same potential to each other; while the drains of both the MOS transistors are commonly connected to each other, and also a common junction point thereof is connected via a current limiting circuit to the control terminal, drain currents are supplied from the control terminal to the respective MOS transistors, and a source of the MOS transistor whose gate-to-source threshold voltage is low is connected via an impedance circuit to the common terminal, and further, a source of the MOS transistor whose gate-to-source threshold voltage is high is connected to the common terminal, whereby a reference voltage is produced from both ends of the impedance circuit, while using a difference between the gate-to-source threshold voltages of the both MOS transistors as a parameter; the comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the reference voltage with the current-detected voltage which is obtained from the current detecting circuit; and the gate controlling MOS transistor controls a gate voltage of the power MOS transistor upon receipt of the comparison output of the comparing circuit.
Since the reference voltage which constitutes an operation reference of a current control operation such as an overcurrent protection can be set to a low voltage under stable condition by employing the above-described first means, a voltage loss occurred between the output terminal and the common terminal can be reduced, and a user-sided apparatus load required for executing ON/OFF operation can be reduced, and furthermore, a current control operation such as an overcurrent protection can be correctly carried out under stable condition.
A second means is featured by that in the first means, the semiconductor integrated circuit includes a current detecting MOS transistor connected to the power MOS transistor in a current mirror manner, for supplying the current in a preselected mirror ratio; and the current detecting circuit converts a mirror current flowing through the current detecting MOS transistor into a voltage corresponding to the mirror current. In accordance with this second means, a load current can be correctly converted into the voltage so as to detect this load current, while the current detecting circuit is not employed between the output terminal and the common terminal.
A third means is featured by that in either the first means or the second means, all of the transistors which are formed on the semiconductor substrate are equal to n-channel MOS transistors. As a result, the semiconductor integrated circuit can be manufactured in a simple manufacturing process and in low cost, as compared with that of a CMOS semiconductor integrated circuit.
A fourth means is featured by that all of the transistors which are formed on the semiconductor substrate are equal to p-channel MOS transistors. Also, in this case, the semiconductor integrated circuit can be manufactured in a simple manufacturing process and in low cost, as compared with that of a CMOS semiconductor integrated circuit.
A fifth means is featured by that in the first means, the comparing circuit contains a latch function capable of self-holding an output state thereof. As a result, the interrupt condition occurred due to the overcurrent can be held until the application of the control voltage is once removed.
A sixth means is featured by that in the first means, a resistance element is series-connected to the gate of the power MOS transistor, and also both the drain and the source of the gate controlling MOS transistor are connected between a gate-sided terminal of the gate series resistance element and the common terminal, whereby a circuit for controlling a gate voltage of the power MOS transistor is formed. As a result, the control operation for controlling the gate voltage of the power MOS transistor can be firmly and simply carried out by receiving the comparison result of the comparing circuit.
A seventh means is featured by that in the first means, the reference voltage which is produced based upon either the gate-to-source threshold voltages of the one pair of the MOS transistors or a difference between the gate-to-source threshold voltages in such a manner that the reference voltage generating circuit generates a preselected reference voltage by receiving an input voltage lower than such a minimum operation voltage of the comparing circuit. As a result, when the control voltage is externally applied, such a sequence operation can be automatically carried out, by which before the comparing circuit commences the operation, the reference voltage control apparatus outputs a predetermined reference voltage.
An eighth means is featured by that in the first means, the current limiting circuit is formed by a polycrystal silicon layer having a high resistance value. As a result, the current limiting circuit can be relatively easily formed.
A ninth means is featured by that in the first means, the power MOS transistor is formed by employing a polycrystal silicon gate. As a result, the semiconductor integrated circuit can be manufactured without changing the manufacturing process of the known MOS integrated circuit.
A tenth means is featured by that in the first means, impurity density of channel layers of the paired MOS transistors which constitute the reference voltage generating circuit is made different from each other, whereby different gate-to-source threshold voltages from each other are applied to the paired MOS transistors. As a result, the MOS transistor having the higher precision threshold value can be manufactured.
An 11-th means is featured by that in the first means, ratios of gate widths to channel lengths of the paired MOS transistors which constitute the reference voltage generating circuit are made different from each other, whereby different gate-to-source threshold values are applied to the paired MOS transistors. As a result, the MOS transistors having the different threshold values can be manufactured only by changing the design, not by changing the manufacturing process.
A 12-th means is featured by that in the first means, a resistor is series-connected to the drains of the paired MOS transistors which constitute the reference voltage generating circuit, whereby different gate-to-source threshold values are equivalently applied to the paired MOS transistors. As a result, while the same MOS transistors are employed, such MOS transistors having virtually different threshold voltages can be manufactured.
A 13-th means is featured by that in the first means, a temperature detecting circuit operated in response to a control voltage applied to the control terminal; a latch circuit which inverts an output state thereof so as to self-hold the state in the case that the temperature detecting circuit detects a temperature higher than, or equal to a predetermined temperature; and a gate voltage controlling MOS transistor for controlling the gate voltage of the power MOS transistor upon receipt of the held output of the latch circuit at the gate thereof are formed on the semiconductor substrate. As a result, the interrupt condition which occurs due to abnormal temperature increase can be maintained until the application of the control voltage is once removed.
A 14-th means is featured by that in the first means, in the reference voltage generating circuit, a back gate of one of the MOS transistor whose source is connected via the impedance circuit to the common terminal is connected to the common terminal at the same potential. As a consequence, both the stability characteristic and the reproducibility characteristic of the reference voltage can be improved, while eliminating the adverse influence caused by the stray bipolar transistor within the semiconductor substrate.
A 15-th means is featured by that in the first means, the output terminal is derived from the semiconductor substrate, and the common terminal is derived from an electrode layer on an insulating film which is formed on the power MOS transistor. As a consequence, the respective terminals can be derived in a simple manner.